1. Technical Field
This invention relates to improvements in a signal electrode driver with internal RAM that is used in a liquid crystal display device.
2. Background Art
A known prior art method of transferring display data from a microprocessor unit (MPU) to a single electrode drive circuit (X driver) in a liquid crystal display module (liquid crystal panel or LCD panel) in a simple matrix type of liquid crystal display device uses an X driver with internal RAM. With this method, the display data is sequentially transferred to the X driver by a shift clock, and this display data is temporarily written to the internal RAM. The display operation is performed by simultaneously reading out the display data for one scan line. With this method, display data is stored in the internal RAM of the X driver. Therefore, if there are no changes in the display, the display can be refreshed by reading out the display data from the internal RAM without having to transfer new display data to the X driver. This makes it unnecessary to transfer display data by the shift clock when there are no changes in the display, enabling low-power operation.
An example of the configuration of a prior art X driver with internal RAM is shown in FIG. 14. This X driver comprises a row address counter decoder 904, a timing circuit 906, a data input control circuit 908, a chip enable control circuit 910, a bidirectional shift register 912, data register 914, a frame memory (internal RAM) 916, a latch circuit 918, a level shifter 920, and a voltage selector 922. The row address counter decoder 904 functions to sequentially select one line at a time from the frame memory 916. Initialization of the selection address is based on a YD signal, and the selection address is incremented when data write to the frame memory 916 ends after the falling edge of an LP signal. The timing circuit 906 has various functions, such as control of the row address counter decoder 904 on the basis of a shift clock XSCL. The data input control circuit 908 fetches display data D.sub.0 to D.sub.n from the MPU and transfers the fetched data to the data register 914. The chip enable control circuit 910 implements automatic power-saving for individual chips, when a plurality of chips are used, on the basis of enable signals CEI and CEO. The bidirectional shift register 912 outputs a control signal to the data register 914 for writing display data D.sub.0 to D.sub.n to the data register 914. The order in which the display data is fetched to the data register 914 is inverted by an SHL signal. The data register 914 controls the writing of the display data to the frame memory 916, and data is written to the frame memory 916 at the falling edge of the LP signal.
The latch circuit 918 reads from the frame memory 916 display data for the row address selected by the row address counter decoder 904 at the falling edge of the LP signal, and outputs it to the level shifter 920. The level shifter 920 is a circuit for converting the voltage levels of signals from a logical power voltage level (V.sub.DD or V.sub.SS) to a power voltage level for the liquid crystal drive (V.sub.o to V.sub.s). The voltage selector 922 functions to select from voltages V.sub.o to V.sub.s for driving signal electrodes X.sub.1 to X.sub.m. The selection of one of V.sub.o to V.sub.s is determined by the display data and the FR signal which acts as a signal for alternating liquid crystal drive.
In the above described example of the prior art, the row address counter decoder 904, the timing circuit 906, the data input control circuit 908, the chip enable control circuit 910, the bidirectional shift register 912, the data register 914, the frame memory (internal RAM) 916, and the latch circuit 918 are located in a low-voltage-amplitude operating portion 901, as shown in FIG. 14, and the level shifter 920 and the voltage selector 922 are located in a high-voltage-amplitude operating portion 902. A voltage difference between a power voltage on a high-potential side and a power voltage on a low-potential side within the low-voltage-amplitude operating portion 901 is small, but a voltage difference between a power voltage on a high-potential side and a power voltage on a low-potential side within the high-voltage-amplitude operating portion 902 is large.
With this prior art example, the size of the RAM (the frame memory 916) in the X driver increases as the size of the LCD panel increases, so that the chip area would also increase if nothing further were done. In order to prevent any increase in the chip area, the use of a high-resistance type of RAM has been considered as the internal RAM, instead of a full-CMOS type of RAM. A full-CMOS type of RAM cell comprises a p-channel transistor and an n-channel transistor, but a high-resistance type of RAM cell comprises a high-resistance element and an n-channel transistor. Since there is no p-channel transistor within each RAM cell in the high-resistance type of RAM, there is no need to provide the element separation that would be necessary between a p-channel transistor and an n-channel transistor, which leads to a huge reduction in area. Thus, in order to reduce the chip area and lower the cost of the device, it is preferable to use a high-resistance type of RAM as the internal RAM.
In order to ensure that a liquid crystal drive device can be used in a liquid crystal display device in equipment such as portable electronic appliances, it is also preferable that power consumptions are reduced, and thus there is a tendency to reduce the power voltages that are used. This means that further decreases in the power voltages of the low-voltage-amplitude operating portion 901 of the X driver are continuing to be implemented. However, in order to ensure a complete lowering of these voltages, the power voltages of the internal RAM (the frame memory 916) in the low-voltage-amplitude operating portion 901 of the X driver must be reduced.
While on the one hand it is necessary to employ a high-resistance type of RAM as the internal RAM in order to enable reductions in chip area, the problem arises that the power voltages of the internal RAM must also be reduced in order to reduce the power voltages of the low-voltage-amplitude operating portion 901 and thus enable reductions in the power consumptions of the resultant devices.
However, the high-resistance type of RAM cell has problems in that read and write errors occur if the operating power voltage is less than 3.0 V, whilst data hold errors and thus retention errors (data changing errors) occur if it is less than 1.5 V. These problems will now be discussed in detail with reference to FIG. 15.
FIG. 15 shows an example of the configuration of a high-resistance (high resistance loading) type of RAM cell. This RAM cell comprises drive n-channel transistors 801 and 802 (T1 and T2) and high-value resistors 805 and 806 (R1 and R2). These components T1, T2, R1, and R2 form a data-hold unit. This RAM cell also comprises n-channel transistors 803 and 804 (T3 and T4) used as transmission gates. The transistors T3 and T4 turn on when a word line WL 804 is high, to transfer the potentials of a bit line BL 808 and a bit line bar-BL 809 to the data-hold unit configured of components T1, T2, R1, and R2.
The basic operation of this RAM cell will now be described. For data write, the transmission gates T3 and T4 turn on and the potentials of BL and bar-BL (the inverse of BL) are transferred to the data-hold unit. At this point, if it is assumed that BL is high and bar-BL is low, the potentials of the points M1 and M2 are also high and low, respectively. If the potential of point M1 goes high, transistor T2 turns on to stabilize the potential of point M2 at low. Since the potential at point M2 is low, transistor T1 turns off, stabilizing the potential of point M1 at high. The potential of point M1 is pulled up high by the high-value resistor R1 and that of point M2 is fixed at low by the transistor T2, even if the transmission gates T3 and T4 turn off thereafter, so that the potentials of points M1 and M2 are held. This implements the data write operation. For data read, the transmission gates T3 and T4 turn on and the potentials of points M1 and M2 are transferred to BL and bar-BL. These potentials are then detected by means such as sense amplifiers, to implement the data read operation.
The description now concerns an erroneous write operation. In a write, write signals are transferred via the transmission gates T3 and T4. During this time, a state occurs in which the voltage of the write signal drops by an amount equal to the threshold voltage V.sub.th of the n-channel transistor of each transmission gate. If a write in which BL is high and bar-BL is low is considered, the potential at point M1 drops from high level by the amount of the threshold voltage V.sub.th of transistor T3. This would not cause any problem if the potential at point M1 remains at a high enough level that the transistor T2 stays on. However, the potential at point M1 drops as the operating power voltage drops, and thus the transistor T2 will no longer be kept on by the potential at point M1 if the operating power voltage falls below a predetermined voltage. As a result, even if a low level is written to point M2 by the bar-BL side, the potential of point M2 will not remain stably at low, and thus an erroneous write operation will occur.
The description now concerns an erroneous read operation. In a read, the transmission gates T3 and T4 are turned on after BL and bar-BL are pre-charged to high, before the read occurs. In this case, assume that M1 is high and M2 is low at this point. If so, the potential at point M2 rises slightly as the potential at point M1 drops by the threshold voltage V.sub.th of the transistor T3. As a result, the transistor T2 which was in the on state moves slightly toward the off state and, at the same time, the transistor T1 which was in the off state moves slightly toward the on state. If the operating power voltage drops, the transistor T2 moves even further toward the off state and the transistor T1 moves even further toward the on state, and this could lead to a phenomenon in which the on/off states invert, and an erroneous read operation will occur. If the operating power voltage is lowered in such a manner, the impedance balance between the loads R1 and R2 and the transistors T1 and T2 will be destroyed, and variations in the threshold voltages Vth of the transistors will greatly affect stable operation. Thus a lowering of the operating power voltage will make it difficult to ensure a wide operating margin.
There is a problem with the above prior art example in that it is not possible to satisfy demands for a smaller chip area enabled by the use of high-resistance type of RAM as well as demands for lower power consumptions of the device enabled by lowering the voltage of the low-voltage-amplitude operating portion 901.
This problem is the same as the problem that occurs with a method called the multiple line selection drive method. This multiple line selection drive method has already been described by the present applicants in Japanese Patent Application Nos. 5-515531 and 5-152533.